Overview
RTL IP Information
Design files
RTL source files or encrypted codes
Language (RTL)
SystemVerilog
Interfaces
AXI4-LITE for input and output
Documentation
User guide
FPGA vendors
Xilinx
Devices verified
Virtex UltraScale+
Memory files (RAM/ROM)
Vendor specific models with .mif files (for ROM)
Polar Encoder/Decoder
3GPP compliant Polar encoding/decoding core IP
LDPC Encoder/Decoder
3GPP compliant LDPC encoding/decoding core IP
5G NR SCI (Sidelink Control Information) Encoder/Decoder
3GPP compliant 5G NR SCI encoding/decoding chain IP for high-performance 5G-V2X systems
5G NR SL-SCH (Sidelink Shared Channel) Encoder/Decoder
3GPP compliant 5G NR SL-SCH encoding/decoding chain IP for high-performance 5G-V2X systems
LTE SCI (Sidelink Control Information) Encoder/Decoder
3GPP compliant LTE SCI encoding/decoding chain IP for high-performance LTE-V2X systems
LTE SL-SCH (Sidelink Shared Channel) Encoder/Decoder
3GPP compliant LTE SL-SCH encoding/decoding chain IP for high-performance LTE-V2X systems
